1. Field of the Invention
The present invention relates to a semiconductor testing device and a method for testing semiconductor memories; in particular a device and method having a built-in self-tester and a linear feedback shift register for testing semiconductor memories.
2. Discussion of Related Art
BIST (built-in self test) is a technique for testing embedded memory using a circuit having a test algorithm. A conventional BIST circuit is shown in FIG. 1. As shown, the BIST circuit 100 includes an address generator 120 for generating addresses to access the locations of Memory 150. The Data Generator 120 generates the data to be tested, and a comparator 140 compares data read from Memory 150 against the data written into the memory. BIST controller 110 typically includes a stored program which when executed, applies the proper control signals to the address generator 120, data generator 130, and comparator 140 to test the memory 150. BIST controller 110 also receives the compared data from comparator 140 and determines whether the test has passed or failed.
A March test algorithm is commonly employed as the test algorithm stored in the BIST controller for testing the embedded memory. The March test algorithm implements a test sequence which tests each bit of each location in the memory by causing both a xe2x80x980xe2x80x99 and a xe2x80x981xe2x80x99 value to be written to and read from the memory. The address to the memory are incremented and decremented in sequential order until all locations are tested. The March test sequence is:
(WD)↑(RD, WDxe2x80x2)↑(RDxe2x80x2, WD)↓(RD, WDxe2x80x2)↓(RDxe2x80x2, WD)(RD)
Wherein the symbols ↑, ↓, and  denote directions of counting addresses of: xe2x80x9cupxe2x80x9d (address increment) xe2x80x9cdownxe2x80x9d (address decrement), and xe2x80x9cup or downxe2x80x9d (increment or decrement), respectively. The symbols W and R represent writing and reading, respectively. D is a data value, either a xe2x80x98O xe2x80x99 or xe2x80x981xe2x80x99 and Dxe2x80x2 denotes the opposite of D. WD means a writing operation with data D and RDxe2x80x2means a reading operation with Dxe2x80x2. The parenthesis xe2x80x9c( )xe2x80x9d denotes the operations which are carried out for all the addresses and if more than one operation is within the parenthesis, both operations are carried out at the same address location. For example, xe2x80x9c(RD, WDxe2x80x2)xe2x80x9d means D is read out of and Dxe2x80x2 is written into the same location before the address is changed. The March test method detects stuck-at faults at each cell, but cannot detect coupling and address faults. See xe2x80x9cAn Effective BIST Scheme for Ring-Address Type FIFOs.xe2x80x9d By Y. Zodan, A. J. Van De Goor, and Ivo Schanstra, IEEE Int. Test Conference, Washington D.C., pp. 378-387, Oct. 1994.
U.S. Pat. No. 5,706,293 to Kim et al. describes a test method which detects address faults and coupling faults in addition to the stuck-at faults detected by the March test algorithm. The addressing described in the xe2x80x98293 Patent is unidirectional (single-order address). The xe2x80x98293 patent describes use of xe2x80x98Address Data Backgroundsxe2x80x99 as test data which tests all memory locations for the above-described faults. The Address Data Backgrounds (ADBs) are pseudo-random data which can be generated by a linear feedback shift register (LFSR). The xe2x80x98293 patent discloses a test pattern of:
(WD), (RD, WDxe2x80x2), (RDxe2x80x2, WD), (RD).
ADB is defined in the xe2x80x98293 patent as a union of all the data that two (2) random cells having mutually different addresses can have. In the xe2x80x98293 test method, an ADB from a group is selected as an initial data written into all the locations of the memory. Upon reading the ADBs first written into all the locations, the inverse or opposite value of the same ADB is written into all the locations of the memory. Addressing of the memory is by sequential incrementation. The inverted ADB data is read and when the inverted data is correctly read, data from the same ADB group is written to and read from each location of the memory again. These steps are repeated for each of the Address Data Backgrounds. In the xe2x80x98293 test method, counters such as carry propagation adder, carry safe adder, or ripple counter can be used to provide a unidirectional count from zero to the most significant location of the memory. The xe2x80x98293 patent is commonly assigned to the applicant and the disclosure of U.S. Pat. No. 5,706,293 is incorporated by reference herein.
Referring again to FIG. 1, the address generator 120 in BISTs typically is a counter which is capable of repeatedly counting up or counting down sequentially. A sequential up-down counter is used to implement the March test algorithm. An up-down counter sequentially counts up or down by adding or subtracting one to or from the previous count. Propagation half adders are commonly used to add or subtract to the count. This requires propagating a carry from the least significant bit (LSB) to the most significant (MSB) of an address string. The time of propagation of the carry from the LSB to the MSB of all the address bits represent the cycle time which must be allocated for each test cycle of the BIST tester. Thus, the larger the memory capacity, the wider the address, and the cycle time needed for the address generator/counter must necessarily increase.
A problem is encountered when a BIST circuit is used to test a high capacity memory at operational speed, i.e., at the operating speed of the CPU. Recently, CPUs that operate at 1.5 Ghz are widely available. In order to test a high capacity memory at operational speed, the conventional up-down counter cannot be employed because the carry cannot propagate through the entire counter within the cycle time of a CPU cycle at operational speed.
Further, a BIST circuit is typically embedded within the memory on the same chip. To test a higher capacity memory, the address is wider or has more bits and more adders are needed in the up-down counter. This results in an increased size requirement for the BIST circuit, compromising valuable real estate of the semiconductor chip.
Accordingly, a need exists for a BIST circuit and method for testing semiconductor memories which avoid the above-discussed problems. The desired BIST circuit and method should be capable of generating addresses for testing all locations of the memory at normal CPU operational speed and the BIST circuit does not occupy a large chip area.
According to an aspect of the present invention, a semiconductor device is provided for testing a memory having N locations, the device comprising: a Linear Feedback Shift Register (LFSR) for creating unidirectional pseudo-random (log2N)-bit address patterns, the address patterns being used as addresses for memory locations to be tested; a data generator for generating data patterns based on the address patterns generated by the LFSR, said data patterns are grouped into (log2N)+1 Address Data Background (ADB) groups, each of the ADB groups having N locations, said data patterns for use as data input to the memory for testing; a comparator for comparing the data input to the memory against the data output from the memory for data integrity verification; and a built-in self test (BIST) controller, operatively connected to the LFSR, data generator, and comparator, for controlling testing of the memory.
Preferably, the data patterns include in each location data represented by a first logic level during a first test step and a second logic level during a second test step, wherein one of the ADB groups includes data represented by logic level low in the entire width of each location, the entire width being one or more bits.
According to a preferred embodiment of the invention, (log2N) groups of the (log2N)+1 ADB groups include at each location corresponding to an address generated by the LFSR, data having the same logic level as the logic level of address data in a predefined bit position of the address.
Preferably, each of the succeeding (log2N) ADB groups of the (log2N)+1 ADB groups is divided into a first subgroup and a second subgroup, wherein locations in the first subgroup are tested with data having a first logic level and locations in the second subgroup are tested with a second logic level. The last of the succeeding ADB groups preferably having data with the first logic level in every other location. Alternatively, locations in each of the succeeding ADB groups are divided into two subgroups until the last of the ADB groups has N subgroups.
The BIST controller according to an aspect of the present invention includes stored program codes which when executed, applies the addresses generated by the LFSR in a predefined sequence, wherein one predefined sequence is:
WD, (RD, WDxe2x80x2), (RDxe2x80x2, WD), RD.
A method according to the present invention is also provided for testing a memory having N locations embedded in a semiconductor device, comprising the steps of: creating unilateral pseudo random (log2N)-bit LFSR address patterns using a LFSR, the LFSR address patterns for use as addresses for addressing locations of the memory to be tested; generating data patterns for use as test data for inputting to locations of the memory addressed by the LFSR address patterns, the test data being based on address data of the LFSR address patterns.
The method preferably includes test data represented by a logic level which is the same as the logic level of a predefined bit of a corresponding LFSR address pattern.
The method according to a preferred embodiment of the invention further includes the step of grouping the data patterns in (log2N)+1 ADB groups, wherein each of (log2N) ADB groups of the (log2n)+1 ADB groups is further divided into two subgroups, one subgroup having a low logic level data and the other subgroup having a high logic level. The last of the (log2N) ADB has N subgroups.